In this post I will talk about the Junction Field Effect Transistor, or in short, the JFET. This device is actually a unipolar device, which basically means that it has a pretty quick way of controlling the flow of current between its two electrodes.
This happens because of an electric field that kicks in when we apply a reverse bias to the pn-junction inside the JFET.
It is like having a gatekeeper that decides how much current gets to pass through based on the electric field’s influence.
Now, if we recall our Bipolar Junction Transistor (BJT) tutorials, we learned that the output Collector current in a BJT is directly tied to the input current that flows into its Base terminal.
This relationship is what makes the bipolar transistor operate as a “CURRENT” device (we often refer to this as the Beta model).
Basically it allows us to use a smaller input current to control or switch on a much larger load current.
On the other hand, we have the Field Effect Transistor or the FET in short, which unlike our BJT buddies, FETs are all about voltage! They use the voltage applied at their input terminal, which we call the Gate, to manage how much current flows through them.
This means that the output current is proportional to the input voltage instead of current in FETs.
Since their operation depends on an electric field created by that input Gate voltage—hence the name “field effect”—we can think of Field Effect Transistors as “VOLTAGE” operated devices.
You may find that an FET which is a three-terminal unipolar semiconductor has characteristics which are quite similar to those of its Bipolar Transistor (BJT) counterparts.
For instance FETs just like BJTs have high efficiency, instant operation, robustness, and affordability. Because of these great features, they can be used in a wide variety of electronic circuit applications as substitutes for their equivalent bipolar junction transistor cousins. It is like having a reliable alternative that gets the job done just as well!
One great aspect about Field Effect Transistors is that they can be manufactured in much smaller packages than an equivalent BJT.
This compact size combined with their low power consumption and minimal power dissipation makes them perfect for use in integrated circuits, especially in the CMOS range of digital logic chips that we see in so many devices today.
Now from our previous BJT lessons we remember that there are two basic types of bipolar transistor (BJT) constructions which are NPN and PNP. These terms describe the physical arrangement of the P-type and N-type semiconductor materials used inside their construction.
The same concept applies to FETs also, which also have two primary classifications, the N-channel FET and the P-channel FET.
When we break down a field effect transistor construction, we realize an important fact that it is a three-terminal device which has no PN-junctions within the main current-carrying path between the Drain and Source terminals.
These terminals correspond functionally to the Collector and Emitter of a bipolar transistor. The pathway where current flows between these two terminals is referred to as the “channel,” which can be made from either P-type or N-type semiconductor material.
When we talk about controlling the current flowing through the channel in a Field Effect Transistor, it means how we can control the voltage that we apply to the Gate. This is where things get interesting!
We know that BJTs are called “Bipolar” because they operate with both types of charge carriers, holes and electrons.
But when we see the Field Effect Transistor we find that these devices rely solely on one type of charge carrier, either electrons in the case of an N-channel FET or holes for a P-channel FET. So it is a bit more specialized in that sense.
One of the standout advantages of Field Effect Transistors compared to their bipolar transistor cousins is their input impedance, denoted as Rin.
This input impedance is super high, think thousands of Ohms, while BJTs tend to have a much lower input impedance. What does this mean for us? Well, this high input impedance makes FETs really sensitive to input voltage signals, which actually looks great for precision applications.
But there is a problem, because of this high sensitivity, it also makes them quite vulnerable to damage from static electricity. So, we have got to be careful while physically handling FETs!
When it comes to types of Field Effect Transistors, there are two main types, the Junction Field Effect Transistor (JFET) and the Insulated-gate Field Effect Transistor (IGFET). You might recognize the IGFET better as the Metal Oxide Semiconductor Field Effect Transistor or MOSFET for short.
Understanding The Junction Field Effect Transistor
Previously we talked about how a bipolar junction transistor is made up of two PN-junctions that sit right in the main path where the current flows between the Emitter and Collector terminals.
Now, let us talk about the Junction Field Effect Transistor, which we often call JUGFET or JFET for short. Unlike its bipolar cousin, an FET does not have any PN-junctions at all. Instead it features this slim slice of semiconductor material that has high resistivity, think of it as a “Channel.”
This Channel can either be made from N-type or P-type silicon, and it is where the majority carriers get to concentrate and flow through. On the both ends of this Channel, we find two ohmic electrical connections known as the Drain and the Source.
When it comes to JFETs, there are basically two main class: the N-channel JFET and the P-channel JFET. For the N-channel version, the Channel is doped with donor impurities. What this means is that when current flows through this Channel, it’s actually negative because it’s carried by electrons—hence why we call it the N-channel.
Similarly when we look at the P-channel JFET, we find that its Channel is doped with acceptor impurities. This means that the current flowing through this Channel is actually positive, hence the name P-channel—because it is carried by holes instead of electrons.
Now if we compare N-channel JFETs to their P-channel variant, we notice something interesting, the N-channel JFETs have a higher channel conductivity, which basically means they have lower resistance.
Why is that? It is because electrons can move around more freely in a conductor than holes can. So, in terms of efficiency, N-channel JFETs really take the cake when it comes to conducting electricity compared to P-channel ones.
Now, as we have mentioned before, there are those two ohmic electrical connections at either end of the Channel, which we call the Drain and the Source. But here is where it gets a bit more interesting, inside this Channel, there is actually a third electrical connection known as the Gate terminal.
This Gate can also be made from either P-type or N-type material, and it forms a PN-junction with the main Channel.
To help us visualize things better, let us take a look at how the connections of a junction field effect transistor stack up against those of a bipolar junction transistor in the comparison below.
Table Showing the Comparison Between the BJT and JFET Pinout Terminals
| Bipolar Transistor (BJT) | Field Effect Transistor (FET) |
|---|---|
| Emitter – (E) | Source – (S) |
| Base – (B) | Gate – (G) |
| Collector – (C) | Drain – (D) |
Below, we have illustrated the symbols and fundamental construction details for both types of Junction Field Effect Transistors (JFETs).
The semiconductor “channel” of the Junction Field Effect Transistor, or JFET acts like a resistive pathway that allows a voltage, which we call VDS, to push a current, referred to as ID, through it. What is really cool about this setup is that the JFET can conduct current just as easily in either direction.
Since the channel has a resistive nature, we end up with a voltage gradient along its length. This means that as we move from the Drain terminal to the Source terminal, the voltage gradually becomes less positive.
Now, because of this arrangement, we find that there is a high reverse bias at the Drain terminal while the Source terminal has a lower reverse bias.
This difference in bias creates what we call a “depletion layer” within the channel, and interestingly enough, the width of this depletion layer increases as the bias gets stronger.
The amount of current that flows through the channel between the Drain and Source terminals is actually controlled by a voltage that we apply to the Gate terminal.
This Gate is reverse-biased and here is where it gets specific, for an N-channel JFET this Gate voltage is negative but for a P-channel JFET, it is positive.
One important thing we should note is how JFETs differ from Bipolar Junction Transistors (BJTs). When the JFET junction is reverse-biased, we find that the Gate current is practically zero. In contrast, with the BJTs there is always some Base current flowing that is greater than zero.
How to Bias an N-channel Junction Field Effect Transistor
If we look at the cross-sectional diagram above, we see that it illustrates an N-type semiconductor channel.
This channel has a P-type region called as the Gate, which is actually diffused into the N-type channel.
This creates a reverse-biased PN-junction, and it is this junction that gives rise to the depletion region around the Gate area when there are no external voltages applied. Because of this characteristic, we often call JFETs depletion mode devices.
Now, this depletion region is quite interesting because it produces a potential gradient that varies in thickness around the PN-junction.
What this means for us is that it restricts the flow of current through the channel by effectively reducing its width, which in turn increases the overall resistance of the channel itself.
As we examine this setup more closely, we can see that the most depleted part of this region is located between the Gate and the Drain, while the area that is least depleted is found between the Gate and the Source.
Interestingly, when we do not apply any bias voltage (which means we are at zero voltage), the JFET’s channel can still conduct because the depletion region is almost nonexistent—essentially, it has near-zero width.
When there is no external Gate voltage applied (so VG = 0), and we apply a small voltage (VDS) between the Drain and Source, we can expect to see maximum saturation current (IDSS) flowing through the channel from Drain to Source.
This current is only limited by that small depletion region surrounding the junctions.
Now, if we decide to apply a small negative voltage (-VGS) to the Gate, something really interesting happens: the size of that depletion region starts to increase.
As it grows, it reduces the effective area of the channel, which consequently decreases the current flowing through it—a bit like giving it a gentle squeeze.
So by applying this reverse bias voltage, we are increasing the width of the depletion region, which in turn reduces how much current can flow through the channel.
Since our PN-junction is reverse-biased, very little current actually flows into the gate connection.
As we make that Gate voltage (–VGS) even more negative, we will notice that the width of the channel continues to shrink until eventually no current flows at all between the Drain and Source.
At this point, we say that the FET is “pinched-off,” which is somewhat similar to what happens in the cut-off region for a BJT.
The specific voltage at which this channel closes down is referred to as the “pinch-off voltage” (VP).
Understanding the Pinched-off Region in a Junction Field effect Transistor Channel
In this pinch-off region, we find that the Gate voltage VGS, plays a crucial role in controlling the current flowing through the channel.
Interestingly, the voltage VDS has little to no impact on this current at all. What this means for us is that the FET behaves more like a voltage-controlled resistor.
When VGS is at zero, the resistance is also zero, allowing maximum current to flow. On the flip side when the Gate voltage becomes very negative, we reach what we call maximum “ON” resistance (RDS). Under normal operating conditions, we should always keep the JFET gate negatively biased in relation to the source.
It is really important that we never apply a positive Gate voltage. If we do, all of the channel current will end up flowing into the Gate instead of heading towards the Source, which can lead to damage to the JFET—definitely something we want to avoid!
Now when it comes to closing the channel, here is what happens, if there is no Gate Voltage (VGS), we can increase VDS from zero. Conversely, if we have no VDS applied, we can decrease the Gate control negatively from zero. We can also vary both VDS and VGS together.
Next, let us talk about the P-channel Junction Field Effect Transistor. It operates in a very similar way to the N-channel JFET that we just discussed but there are a couple of key differences. First, the channel current is positive because it is carried by holes instead of electrons, second, we need to reverse the polarity of the biasing voltage.
When we look at the output characteristics of an N-channel JFET with the gate short-circuited to the source, we can see some interesting behavior, as given below:
Analyzing the Output characteristic V-I curves of a JFET
This voltage, VGS, which is the voltage applied between the Gate and Source terminals. It’s what’s really making the decisions here, because it controls how much current flows between the Drain and Source terminals.
Meanwhile the VDS is the voltage across the Drain and Source, giving us a sense of the overall voltage difference across the device.
Since the JFET is a type of voltage-controlled device, no current actually flows into the Gate, which is an important characteristic! Instead, all the action is happening with the Source current IS, which flows out of the device and matches up perfectly with the Drain current ID. So in simple terms, IS equals ID, since what flows in has to flow out.
When we look at the characteristic curves, they inform us about four main regions of operation for a JFET, and each has its own unique behavior:
- Ohmic Region: Here, VGS is set to zero, so the depletion layer in the channel is pretty minimal. This means the JFET acts almost like a voltage-controlled resistor.
- Cut-off (or Pinch-off) Region: This region occurs when the Gate voltage VGS, reaches a point where the JFET behaves like an open circuit with maximum channel resistance.
- Saturation or Active Region: In this region, the JFET conducts quite well, and the current is controlled by the Gate-Source voltage (VGS). The Drain-Source voltage (VDS), on the other hand, barely affects the current.
- Breakdown Region: This is where VDS, the voltage between the Drain and Source, becomes high enough to push the JFET past its limits, causing its resistive channel to break down and allowing uncontrolled current to flow through.
For P-channel JFETs, the curve looks similar but there is a twist: the Drain current ID, actually goes down as the positive Gate-Source voltage VGS, goes up.
Now, when VGS reaches a specific point VP, the Drain current is zero. For normal JFET operation, VGS is biased somewhere between VP and zero. This allows us to calculate the Drain current ID, at any given bias point within the saturation or active region using the appropriate equations, as shown below:
Formula for Calculating Drain Current in Active region
ID = IDSS[1 – (VGS/VP)]2
The Drain current, ID, will always sit somewhere between zero and a maximum level known as IDSS. Zero happens at pinch-off, while IDSS is the peak current the device can handle.
When we have both the Drain current ID and the Drain-Source voltage, VDS, we can then calculate the channel’s resistance, which we call RDS, as given below:
Formula for Calculating Drain-Source Channel Resistance
RDS = ΔVDS / ΔID = 1/gm
In the above formula, gm indicates the “transconductance gain” because the JFET is a voltage controlled transistor, giving us the rate of change of the Drain current with respect to the change in Gate-Source voltage.
What are the Modes Operation of FET’s
Just like the bipolar junction transistor, the field effect transistor (FET), with its three terminals, has the flexibility to operate in three unique modes. Because of this we can hook it up within a circuit in any one of these configurations, depending on what we want to achieve.
Common Source (CS) FET Configuration
In the Common Source FET arrangement which looks same as the common emitter BJT setup, we connect the input signal to the Gate terminal of the FET, while the output signal is extracted from the Drain terminal, as depicted in the diagram above.
This configuration is widely regarded as the most favorable design for using a Field Effect Transistor (FET) due to its ability to deliver high input impedance along with substantial voltage amplification. As a result of these advantageous characteristics, the Common Source amplifiers find extensive application across a wide range of electronic systems.
We often employ this arrangement in audio frequency amplifiers, pre-amplifiers, and various stages that necessitate a high input impedance. It is important for us to note that, given its nature as an amplifying circuit, the output signal will be 180 degrees “out of phase” with respect to the input signal.
This phase inversion is a critical aspect of its operation and can be extremely useful in certain applications where phase relationships are cruciial. Thus the effectiveness of the Common Source configuration in enhancing signal processing capabilities is indeed very nice.
Common Gate (CG) FET Configuration
In the Common Gate FET configuration which is exactly same as our BJT common base arrangement, we apply the input signal to the Source terminal, while the output is extracted from the Drain terminal.
In this setup, the Gate is directly connected to ground (0 volts), as illustrated in the above diagram.
It is important to note that we lose the advantageous high input impedance characteristic present in the previous configuration, instead we find that the common gate exhibits a low input impedance coupled with a high output impedance.
This particular FET configuration proves to be highly beneficial in applications involving high-frequency circuits or in scenarios where impedance matching is essential.
Specifically, it is well-suited for situations where a low input impedance must be matched with a high output impedance.
Furthermore we observe that the output signal remains “in-phase” with the input signal, which can be advantageous in various circuit designs.
Common Drain (CD) FET Configuration
In the Common Drain configuration which resembles our BJT common collector circuit, we apply the input signal to the Gate terminal while the output is derived from the Source terminal.
This particular configuration, often referred to as a “source follower,” possesses a high input impedance and a low output impedance, along with a voltage gain that is nearly unity.
Hnece we utilize this arrangement primarily in buffer amplifiers. Please note that the voltage gain of the source follower configuration is slightly less than unity and we find that the output signal is “in-phase” at 0 degrees with respect to the input signal.
We refer to this configuration as “Common Drain” because there is no available signal at the drain connection, instead, the voltage present, denoted as +VDD, serves merely to provide biasing.
In this context we observe that the output remains in-phase with the input signal, which can be particularly advantageous in various electronic applications. This characteristic makes it an ideal choice for scenarios requiring effective buffering and impedance matching.
Using The Junction Field Effect Transistor as an Amplifier
Just like the bipolar junction transistors (BJTs), we can also use JFETs to create single-stage class A amplifier circuits.
We can simply do this by using a JFET common source amplifier configuration. The characteristics of this configuration are very similar to those of a BJT common emitter circuit.
So the basic principles of amplification remain the same. However JFET amplifiers have an advantage over BJTs due to their high input impedance.
This high input impedance is controlled by the Gate biasing resistive network. This network is formed by resistors R1 and R2, as shown below. This setup makes JFET amplifiers particularly useful when we need to minimize the load on the input source.
How to Bias a Junction Field Effect Transistor Amplifier Circuit
VS = ID RS = VDD / 4
VS = VG – VGS
VG = ( R2 / (R1 + R2) ) VDD
ID = VS / RS = ( VG – VGS ) / RS
In this JFET common-source (CS) amplifier circuit, we employ a class “A” biasing mode which is achieved through a carefully designed voltage divider network consisting of resistors R1 and R2. These resistors work together to establish the desired biasing point for the amplifier.
Mostly, we set the voltage across the source resistor RS, so that it is approximately one-quarter of the supply voltage VDD (or VDD/4). However this is not a strict requirement, any reasonable voltage can be chosen based on specific design needs.
Once we determine the appropriate RS voltage, we can then proceed to calculate the necessary gate voltage.
Given that the gate current IG is effectively zero, we have the flexibility to set the required DC quiescent voltage simply by selecting appropriate values for resistors R1 and R2. This method allows us to maintain stable operating conditions and ensure the amplifier performs as expected.
The ability to control the Drain current through a negative Gate potential makes the Junction Field Effect Transistor (JFET) particularly valuable for switching applications.
For an N-channel JFET, it is crucial that the Gate voltage remains negative and never becomes positive. If the Gate were to become positively charged, the channel current would mistakenly flow toward the Gate instead of the Drain which could potentially damage the JFET.
The fundamental operating principles for a P-channel JFET are quite similar to those of an N-channel JFET. However the key difference lies in the voltage polarities, which need to be reversed to make it compatible with the P-channel configuration.
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